The present invention is involved in improving waveform of an access control signal in an electronic device mounting semiconductor component that is accessed and a semiconductor component that accesses on a substrate having a wiring layer, and relates to technology effective when applied to a processor board, control board, etc., on which DIMM (Dual Inline Memory Module) mounting, for example, DDR3-SDRAM (Double-Data-Rate3 Synchronous Dynamic Random Access Memory) is populated.
To a clock synchronous memory operated in synchronization with a clock signal represented by DDR3-SDRAM, an enable control signal to indicate that a clock signal or a command and address signal supplied thereto is valid is input together with the clock signal and the command and address signal. When the clock signal and the command and address signal are indicated to be valid by the enable control signal, the clock synchronous memory performs an access operation according to a timing sequence by an internal logic in synchronization therewith. A state where read data and write data are settled in the access operation is notified by a data strobe signal.
For example, in a memory module such as DIMM, a plurality of clock synchronous memories is mounted and the clock synchronous memories are operated synchronously in a parallel manner. For the synchronous operation in a parallel manner, Non-Patent Document 1 (JEDEC Standard No. 21C, Revision 1.0 Release 18A, 4. 20. 18-204-Pin DDR3 SDRAM Unbuffered SO-DIMM Design Specification, page 4. 20. 18-01-4. 20. 11-60) describes that the T-branch structure is employed for the wiring on the module substrate for the clock signal and the command and address signal supplied commonly to a plurality of DDR2-SDRAMs mounted on DIMM. Due to the T-branch structure, it is made easy to make the same in length the signal wirings from the module terminal of DIMM to the clock terminal and the command and address terminal of the DDR2-SDRAMs, respectively. On the other hand, Non-Patent Document 2 (JEDEC Standard No. 21C, Revision 2.5 Release 18, 4. 20. 11-200-Pin DDR2 SDRAM Unbuffered SO-DIMM Design Specification, page 4. 20. 11-01-4. 20. 11-66) referring to the standard of DIMM mounting DDR3-SDRAM describes that the wiring structure for the clock signal and the command and address signal on the module substrate employs the fly-by structure instead of the T-branch structure. The fly-by structure is a structure in which external terminals of a plurality of DDR3-SDRAMs are coupled sequentially in the form of a string of beads, to a signal line that can be traced with a single stroke and its purpose is to give priority to coupling of DDR3-SDRAMs with the shortest distance over isometric wiring. This is because when isometric wiring becomes more difficult as the operation speed becomes faster, the number of times of routing in wiring for equalization in length increases and the quality of signal waveform deteriorates as a result. For non-isometric wirings due to the fly-by structure, leveling control is performed to delay the input timing etc. of a data strobe signal according to the propagation delay of a clock signal etc. supplied by the wiring with the fly-by.